Area Optimization of 8-bit Multiplier Using Gate Diffusion Input Logic
نویسنده
چکیده
Multipliers are used in all modern digital systems and DSP applications. They are used in hardware multiplication to achieve high data throughput. Multipliers are major sources of area consumption and power dissipation in such systems. Reduction in area can be achieved using Booth encoding and Wallace tree technique since they generate partial products efficiently and are most suited for multiplication of signed numbers. Multiplier designed in Gate Diffusion Logic (GDI) logic requires lesser number of devices as compared to CMOS logic. Hence, the proposed multiplier design will substantially reduce the number of devices as compared to CMOS design. This results in area optimization with the consequent reduction in power and delay of multiplier.
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